Download Udemy - Learn VHDL, PLS's and FPGA (Digital Electronic 2) torrent

Udemy - Learn VHDL, PLS's and FPGA (Digital Electronic 2)

Torrent:	Udemy - Learn VHDL, PLS's and FPGA (Digital Electronic 2)
Description:	Learn VHDL, PLS's and FPGA (Digital Electronic 2) Genre: eLearning \| MP4 \| Video: h264, 1280x720 \| Audio: AAC, 44.1 KHz Language: English \| Size: 2.94 GB \| Duration: 8h 42m Modern Digital Design Principles and Techniques What you'll learn Analyze Combinational and Sequential Circuits. Develop VHDL programs for Combinational and Sequential Circuits. Design of the Arithmetic Logic Unit. Design of memory elements. Description A. Course Description: This course gives a detailed study of modern digital design principles and techniques. Topics include: Programmable Logic Devices (PLDs) and Field Programmable Gate Array (FPGA) devices; Design and optimization of arithmetic circuits, and their programming using Hardware Description Language (e.g. VHDL); Timing Diagrams; Design of a Processor and VHDL simulation. B. Course Outcomes: https://TutPig.com
Downloads:	65
Category:	Other /Tutorials
Size:	2.9 GB
Show Files »	[ TutPig.com ] Udemy - Learn VHDL, PLS's and FPGA (Digital Electronic 2) Get Bonus Downloads Here.url (0.2 KB) ~Get Your Files Here ! 1. Introduction 1. Introduction to CAD tools.mp4 (145.4 MB) 1. Introduction to CAD tools.srt (29.5 KB) 1.1 Fundamentals Of Digital Logic With VHDL Design 3rd Edition.pdf (12.2 MB) 1.2 Lecture 1-Introduction to CAD-VHDL-Ch2_ v3.pptx (870.9 KB) 10. VHDL parallel load counters and bus design 1. Parallel Load counters and bus design.mp4 (155.9 MB) 1. Parallel Load counters and bus design.srt (37.2 KB) 1.1 CENG335 Lecture 9 vhdl parallel load counters and bus design - Narrated.pptx (1.3 MB) 11. VHDL code of the bus design with SWAP operation 1. VHDL code of the bus design with SWAP operation.mp4 (227.8 MB) 1. VHDL code of the bus design with SWAP operation.srt (38.9 KB) 1.1 CENG355 Lecture 10 vhdl code of the bus design with swap operation - Narrated.pptx (953.4 KB) 12. Processor Design and its VHDL 1. Simple Processor Design and its VHDL.mp4 (466.4 MB) 1. Simple Processor Design and its VHDL.srt (84.7 KB) 1.1 CENG335 Lecture 11 Processor Design and its VHDL - Narrated.pptx (2.1 MB) 1.2 CENG335-Exercises-Set1.pdf (671.0 KB) 1.3 CENG335-Exercises-Set2.pdf (191.6 KB) 1.4 CENG335-Exercises-Set3.pdf (179.2 KB) 1.5 Exercises_set1_solution_part1.pdf (1.1 MB) 1.6 Exercises_set1_solution_part2.pdf (2.4 MB) 1.7 Exercises_Set2_Solution_TTH.pdf (2.0 MB) 13. Modelsim 1. Modelsim Software Setup Link.html (0.2 KB) 2. Modelsim Tutorial 1.mp4 (128.4 MB) 2. Modelsim Tutorial 1.srt (19.3 KB) 3. Modelsim Tutorial 2.mp4 (189.5 MB) 3. Modelsim Tutorial 2.srt (28.4 KB) 2. Numbers Representations & LUTs, PLDs, FPGA 1. Numbers Representations.mp4 (88.9 MB) 1. Numbers Representations.srt (24.6 KB) 1.1 Lecture 2 - Numbers Repreentation.pptx (1.8 MB) 2. LUTs, PLDs, FPGA.mp4 (111.2 MB) 2. LUTs, PLDs, FPGA.srt (25.4 KB) 2.1 Lecture 2-PLDs- FPGA-Ch3 .pptx (297.4 KB) 3. Half Adders, Full Adders, RCA, CLA 1. HA FA RCA CLA.mp4 (200.1 MB) 1. HA FA RCA CLA.srt (38.7 KB) 1.1 CENG335 Lecture 3 HA FA RCA CLA.pptx (2.9 MB) 4. VHDL Adders Multiplier Narrated 1. VHDL for adders, Multiplier.mp4 (293.8 MB) 1. VHDL for adders, Multiplier.srt (47.1 KB) 1.1 CENG335 Lecture 2 VHDL Adders Multiplier Narrated.pptx (3.3 MB) 5. Multiplexers and Shannon Expansion 1. Multiplexers and Shannon Expansion.mp4 (308.1 MB) 1. Multiplexers and Shannon Expansion.srt (70.5 KB) 1.1 CENG335 Lecture 4 Multiplexers and Shannon Expansion.pptx (2.4 MB) 6. Decoders Arithmetic Comparator Selected signal assignment 1. Decoders, Arithmetic Comparator, Selected signal assignment.mp4 (190.2 MB) 1. Decoders, Arithmetic Comparator, Selected signal assignment.srt (42.5 KB) 1.1 CENG335 Lecture 5 Decoders Arithmetic Comparator Selected signal assignment.pptx (1.7 MB) 7. Conditional statement generate statement 1. Conditional statement, Generate statement, Sequential Assignment, VHDL operators.mp4 (196.3 MB) 1. Conditional statement, Generate statement, Sequential Assignment, VHDL operators.srt (36.3 KB) 1.1 CENG335 Lecture 6 conditional statement generate statement.pptx (2.1 MB) 8. latches flipflops shift and parallel access registers 1. Latches, FlipFlops, parallel access and shift registers.mp4 (116.4 MB) 1. Latches, FlipFlops, parallel access and shift registers.srt (33.8 KB) 1.1 CENG335 Lecture 7 latches flipflops shift and parallel access registers.pptx (998.2 KB) 9. VHDL gated latches flipflops, registers and counter 1. VHDL for Latches, FlipFlops, registers and counters.mp4 (158.4 MB) 1. VHDL for Latches, FlipFlops, registers and counters.srt (33.9 KB) 1.1 CENG335 Lecture 8 vhdl gated latches flipflops, registers and counters.pptx (1.9 MB) Bonus Resources.txt (0.3 KB) files
Added:	2021-10-18 11:05:15
Language:	English
Peers:	Seeders : 8 , Leechers : 8
Tags:	Engineering VHDL Udemy
Release name:	Udemy - Learn VHDL, PLS's and FPGA (Digital Electronic 2)
Trackers:	udp://tracker.torrent.eu.org:451/announce udp://tracker.tiny-vps.com:6969/announce http://tracker.foreverpirates.co:80/announce udp://tracker.cyberia.is:6969/announce udp://exodus.desync.com:6969/announce udp://explodie.org:6969/announce udp://tracker.opentrackr.org:1337/announce udp://9.rarbg.to:2780/announce udp://tracker.internetwarriors.net:1337/announce udp://ipv4.tracker.harry.lu:80/announce udp://open.stealth.si:80/announce udp://9.rarbg.to:2900/announce udp://9.rarbg.me:2720/announce udp://opentor.org:2710/announce